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Evry,
France, May 2002 - Agilent
Technologies Inc. has achieved a new milestone in the integration of
serializer/deserializer (SerDes) channels in application-specific
integrated circuits (ASICs) used in communications applications.
Agilents results are nine times the current standard in SerDes
integration, and are expected to provide manufacturers with tremendous
savings in board space and cost. Agilents
results were achieved by integrating 36 multi-rate SerDes channels
operating at up to 3.125 Gb/s each, on a single CMOS chip. These results
provide a new level of input/output (I/O) performance and integration in a
CMOS process. Until today, the former industry standard was four 3.125 Gb/s
SerDes channels per chip. Agilent
continue to raise the bar in ASIC SerDes integration, said Ernesto
Prestifilippo, Business Development Director, BFi OPTiLAS, As the
distributor for Agilent in Europe, these advancements allow us to provide
customers with savings in power, board space and cost. The
multi-rate ASIC is backward compatible because each SerDes channel is able
to operate at link rates down to 1.5 Gb/s. The device, which incorporates
32 million transistors, can also drive a signal approximately 20 meters
over standard copper cable. Agilent has previously announced a chip with
more than 50 2.5 Gb/s SerDes transmit and receive channels, and another
ASIC with 16 3.25 Gb/s channels. For
more information please contact: Ernesto Prestifilippo, Business
Development Director, BFi OPTiLAS. E-mail
: E.Prestifilippo@bfioptilas.avnet.com About
BFi OPTiLAS For more information visit: www.bfioptilas.avnet.com
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